1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and more particularly to a synchronous semiconductor memory device such as synchronous dynamic RAM in which read and write operations can be performed based on a pair of complementary clock signals.
2. Description of the Related Art
Synchronous semiconductor memory devices are increasingly used for raising the operational speed of the memory devices. Since semiconductor memory devices have also become increasingly greater in memory capacity, there is a tendency that subjecting semiconductor memory devices to dynamic burn-in tests leads to longer test times. In addition, burn-in test systems used for the burn-in test generally includes respective oscillators that cannot meet the high operational speeds of the memory devices, or DUTs (devices under test). To be more specific, the clock frequencies that can be used in the dynamic burn-in tests on semiconductor memory devices are limited. Thus, a reduction in test time requires some contrivance to increase the operational frequencies used inside the semiconductor memory devices during the burn-in test.
FIGS. 1A to 1C show the configuration and operational timing chart of a dynamic RAM (DRAM) described in Japanese Patent Laid-Open Publication No. Hei 11-213696. FIG. 1A is a block diagram of the dynamic RAM. In the drawing, /RAS1 and /CAS1, for example, represents top-barred RAS1 and top-barred CAS1, respectively. More specifically, xe2x80x9c/RAS1xe2x80x9d and xe2x80x9cCAS1xe2x80x9d signals represent a specific row address strobe and a specific column address strobe, both of which are active at the low level thereof. The /RAS1 signal and the /CAS1 signal are input to the dynamic RAM through an n-type transfer gate pair 81 and input buffers 82 and 83. An address key is input to the dynamic RAM through an address key detection circuit 89. The dynamic RAM controls its memory array based on the /RAS1 and /CAS1 signals. The operational mode of the dynamic RAM is set at either one of normal operation mode and test mode, based on the address key.
In the normal operation mode, the address key detection circuit 89 inputs a low level signal to a P-type transfer gate pair 84 and an N-type transfer gate pair 81. The /RAS1 signal is input to a memory array control circuit 87 through the input buffer 82, the P-type transfer gate 84, and a row address decoder 85. The /CAS1 signal is input to the memory array control circuit 87 through the input buffer 83, the P-type transfer gate 84, and a column address decoder 86.
In the test mode, the address key detection circuit 89 inputs a high level signal to the P-type transfer gate pair 84 and the N-type transfer gate pair 81. The /RAS1 and /CAS1 signals are input to a logic circuit 88 through the N-type transfer gate 81.
FIG. 1B is a circuit diagram showing the configuration of the logic circuit 88. The logic circuit 88 generates a /RAS2 signal based on the /RAS1 and /CAS1 signals through an exclusive-NOR gate (hereinafter, referred to as an EXNOR gate) 90. From this /RAS2 signal, the logic circuit 88 generates a /CAS2 signal through a delay circuit 91. The /RAS2 signal and the /CAS2 signal are input to the memory array control circuit 87 through the row address decoder 85 and the column address decoder 86, respectively.
FIG. 1C is a timing chart showing the operation of the logic circuit 88. The /RAS1 and /CAS1 signals have a period of 2 xcexcs.
The rise and fall of the /RAS1 signal lag a predetermined time length behind the rise and fall, respectively, of the /CAS1 signal. The /RAS2 signal traces a waveform having a pulse width of a predetermined time length. The delay circuit 91 delays the input /RAS2 signal by 20 ns to generate the /CAS2 signal. The /RAS2 and /CAS2 signals have a period of 1 xcexcs.
The technology described in the aforementioned publication is such that a conventional burn-in test system is used to reduce the period of the internal clock for reduced test times in the dynamic burn-in tests. In this technology, if the read speed of the dynamic RAM in the test mode is twice that in the normal operation mode, the burn-in test system requires a circuit that can meet the doubled read speed, to compare the read data against the write data for PASS/FAIL evaluation, This raises the cost of the dynamic burn-in test device, and thereby raises the cost for the dynamic RAM.
In view of the foregoing problem in the conventional technology, it is an object of the present invention to provide a synchronous semiconductor memory device having an operational speed in the test mode, which is twice compared to the operational speed in the normal mode to thereby facilitate the PASS/FAIL evaluation in a dynamic burn-in test of the semiconductor memory device.
The present invention provides a synchronous semiconductor memory device including: a memory cell array including a plurality of groups of memory cells, each of the groups including m memory cells for storing m bits of data; a clock signal generator for receiving a pair of complementary signals including first and second clock signals to generate third and fourth clock signals in a normal operation mode, the third clock signal having a rise time substantially in synchrony with a fall time of the first clock signal, the fourth clock signal having a rise time substantially in synchrony with a rise time of the first clock signal, the clock signal generator generating in a test mode a fifth clock signal having a frequency which is double a frequency of the first clock signal; a read/write control circuit for responding to the first clock signal in the normal operation mode to control a read/write operation for the memory cells, the read/write control circuit responding to the fifth clock signal in the test mode to control a read/write operation for the memory cells; a plurality of data latches each disposed for a corresponding one of the m bits, each of the data latches responding to the third and fourth clock signals in the normal operation mode to latch read data from a corresponding one of the memory cells in synchrony with the third clock signal and delivering the latched read data in synchrony with the fourth clock signal; and a bypass circuit for responding to the fifth clock signal to allow the read data to bypass the data latches during the test mode.
According to the synchronous semiconductor memory device of the present invention, the read/write control circuit operates in synchrony with the doubled signal and the bypass circuit bypasses the latches at the read operation in the test mode. This makes it possible to double the operational speed in the test mode without increasing the operational frequency of the burn-in test device